The present invention generally relates to semiconductor devices and fabrication process thereof and more particularly to a semiconductor device including a field effect transistor and fabrication process thereof.
With demand for improvement of performance in semiconductor devices in recent years, there is also a demand of improved performance in the field effect transistors (FET) such as a metal-oxide-semiconductor (MOS) transistor used in such semiconductor devices. Typically, a MOS transistor has a structure in which a source region and a drain regions are formed in a diffusion layer called well formed in a semiconductor substrate in the form of diffusion regions of opposite conductivity type.
In order to improve the resistance of such MOS transistors against noise, there is proposed the use of a so-called triple well structure in which a well used for a device region is formed in a substrate in a manner surrounded by an impurity diffusion region of opposite conductivity type. With such a structure, the well forming the device region is isolated from the influence of other circuits or the semiconductor substrate itself.
In this technology of triple well, it is proposed to provide a terminal outside the triple well and control the potential of the well inside the triple well via a conduction region formed so as to conduct the interior of the triple well with the external terminal (Patent Reference 1).